3D integration of die is an attractive technology to meet future performance needs of integrated circuits. Benefits can be realized in signal bandwidth and latency, power consumption, form-factor, and cost. In addition, 3D technology may facilitate heterogeneous integration, for example III-V materials on silicon (Si) or memory on logic.
3D interconnect technology can be implemented as either die-to-wafer or wafer-to-wafer and each approach has its benefits and limitations. For example, die-to-wafer allows the use of known good die, which can result in yield enhancement of the final die stack. However, die-to-wafer results in lower throughput, as each die needs to be aligned and placed onto the wafer. This process can be especially slow if there are small dies or if a high degree of alignment is required. In comparison, for wafer-to-wafer integration, selection of known good die prior to the bonding process is not possible, but a much higher throughput can be achieved.
Wafer thinning and back-side insulation is a necessary technology component of 3D integration, as it may allow the interlayer distance to be reduced, thereby allowing a higher density of vertical interconnects. In bulk Si, wafer thinning may be challenging as there is no natural etch stop. The final thickness may depend on the thinning process control capabilities and may be limited by the thickness uniformity specifications of the Si removal process.
Moreover, the properties of back-side insulation layer affect the inter-layer performance for chip-to-wafer or wafer-to-wafer integration. With the inter-layer distance being decreased, either substrate coupling or inter-chip coupling effect becomes detrimental to device performance.
In addition, the insulation layer may have interface issues in terms of adhesion to the wafer and may allow drift or diffusion of the metal of the TSV into the insulation layer, which may be a source for Time-Dependent Dielectric Breakdown (TDDB) reliability issue. The insulation layer also has defects such as cracks and has large parasitics.
Furthermore, conventional process use lithography-processes on a backside surface (dual side alignment), and have a limitation in patterning resolution and alignment accuracy for TSV passivation opening between the TSV and the resist opening.